The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with silicides of different thicknesses and of different materials for the drain/source and the gate of the field effect transistor.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension junction 104 and a source extension junction 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension junction 104 and the source extension junction 106 are relatively shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate structure 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate structure 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate structure 118 and the gate dielectric 116.
As the dimensions of the MOSFET 100 are scaled down further, such as 50 nm (nanometers) for the gate length of the MOSFET 100 for example, the depth of the drain extension junction 104 and the source extension junction 106 is also scaled down to about 15-30 nm (nanometers). The depth of the drain extension junction 104 and the source extension junction 106 is desired to be small to minimize short-channel effects in the MOSFET 100 as the gate length of the MOSFET 100 is scaled down, as known to one of ordinary skill in the art of integrated circuit fabrication.
In addition, the depth of the drain contact junction 108 and the source contact junction 112 is also scaled down proportionately. The drain silicide 110 should not reach down to the interface between the drain contact junction 108 and the semiconductor substrate 102, and the source silicide 112 should not reach down to the interface between the source contact junction 112 and the semiconductor substrate 102. Thus, as the depth of the drain contact junction 108 and the source contact junction 112 is scaled down, the thickness of the drain silicide 110 and the source silicide 114 is limited by the decreased depth of the drain contact junction 108 and the source contact junction 112.
In the prior art, the drain silicide 110, the source silicide 114, and the gate silicide 120 are typically formed simultaneously, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, in the prior art, the thickness of the drain silicide 110 and the source silicide 114 is substantially same as the thickness of the gate silicide 120, and the silicide material comprising the drain silicide 110 and the source silicide 114 is substantially same as the silicide material comprising the gate silicide 120. As the depth of the drain contact junction 108 and the source contact junction 112 is scaled down, the thickness of the drain silicide 110, the source silicide 114, and the gate silicide is limited by the decreased depth of the drain contact junction 108 and the source contact junction 112 when the drain silicide 110, the source silicide 114, and the gate silicide 120 are formed simultaneously in the prior art.
In addition, U.S. Pat. No. 5,731,239 to Wong et al. teaches forming a gate silicide that may be comprised of a different silicide material from that of the drain and source silicides, but does not teach forming a gate silicide having a larger thickness than that of the drain and source silicides. U.S. Pat. No. 5,953,612 to Lin et al. teaches forming a gate silicide having larger thickness than that of the drain and source silicides, but does not teach forming a gate silicide comprised of a different silicide material from that of the drain and source silicides. In addition, such prior art does not address minimizing short channel effects in the MOSFET having scaled down dimensions.
Although the thickness of the drain silicide 110 and the source silicide 114 may be limited by the decreased depth of the drain contact junction 108 and the source contact junction 112, a gate silicide with further minimized resistance is desired for minimizing parasitic resistance at the gate of the MOSFET. In addition, for the MOSFET having scaled down dimensions of tens of nanometers, disadvantageous short channel effects may degrade the performance of the MOSFET, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, short channel effects are desired to be minimized.
Thus, a mechanism is desired for fabricating the drain silicide 110 and the source silicide 114 to have a different thickness from the gate silicide 120 and to be comprised of a different silicide material from that of the gate silicide 120 to minimize resistance at the gate of the MOSFET.
Accordingly, in a general aspect of the present invention, the drain silicide and the source silicide are formed separately from formation of the gate silicide. The gate structure is covered with a hardmask dielectric material that prevents formation of a gate silicide with the gate structure during a first silicidation process for formation of the drain silicide and the source silicide. An encapsulating dielectric material covers the drain silicide and the source silicide to prevent further formation of the drain silicide and the source silicide during a second silicidation process for formation of the gate silicide with the gate structure.
In one embodiment of the present invention, in a method for fabricating a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate, a drain extension junction and a source extension junction are formed in the active device area of the semiconductor substrate. Spacers are formed to cover the drain extension junction and the source extension junction and to cover sidewalls of the gate structure. A drain contact junction is formed adjacent the drain extension junction, and a source contact junction is formed adjacent the source extension junction by implanting a contact junction dopant into exposed regions of the active device area of the semiconductor substrate. A hardmask dielectric material is formed to cover a top surface of the gate structure. A drain silicide is formed with the drain contact junction that is exposed, and a source silicide is formed with the source contact junction that is exposed. The drain silicide and the source silicide have a first thickness and are comprised of a first silicide material. The hardmask dielectric material that covers the top surface of the gate structure prevents formation of silicide with the gate structure during formation of the drain silicide and the source silicide.
An encapsulating dielectric material is deposited, in a deposition process using a relatively low temperature of less than about 400xc2x0 Celsius, to cover the drain silicide and the source silicide. The hardmask dielectric material is etched away from the top surface of the gate structure to expose the top surface of the gate structure. A gate silicide is formed with the gate structure, and the gate silicide has a second thickness and is comprised of a second silicide material. The encapsulating dielectric material covering the drain silicide and the source silicide prevents further formation of the drain silicide and the source silicide during formation of the gate silicide.
The first thickness of the drain and source silicides is less than the second thickness of the gate silicide, and the first silicide material of the drain and source suicides is different from the second silicide material of the gate silicide. In this manner, the thickness of the gate silicide is independent of the thickness of the drain and source suicides and is not limited by the decreased depth of the drain and source contact junctions as the dimensions of the MOSFET are further scaled down. A thicker gate silicide and a different gate silicide material decrease parasitic resistance at the gate of the MOSFET for enhanced speed performance of the MOSFET. In addition, because the encapsulating dielectric material is deposited in a deposition process using a relatively low temperature of less than about 400xc2x0 Celsius, short channel effects are minimized for the MOSFET having scaled down dimensions of tens of nanometers.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.